IBM stacks 100 billion transistors in experimental chip
IBM’s new chip stacks two silicon layers to pack 100 billion transistors, doubling capacity without shrinking circuits further, which could extend Moore’s Law and enable more powerful, energy-efficien
IBM just unveiled a chip crammed with 100 billion transistors—twice as many as today’s top chips—by stacking two layers of silicon circuits. The break
Read Full Story at New Scientist →Why This Matters
The breakthrough signals a potential resurgence in Moore’s Law, which has slowed in recent years due to the physical limitations of traditional silicon scaling. By vertically stacking transistor layers rather than shrinking them horizontally, IBM is pushing the boundaries of computational density without resorting to unproven alternatives like 2D materials or quantum architectures.
Background Context
Moore’s Law, once a self-fulfilling prophecy for the semiconductor industry, has faced mounting obstacles as transistors approach atomic scales. The $10 billion-plus cost of next-generation fabs and the diminishing returns of planar CMOS have forced chipmakers to explore vertical integration, hybrid bonding, and other unconventional techniques to sustain progress.
What Happens Next
If IBM’s approach proves manufacturable at scale, it could reignite a new phase of Moore’s Law without requiring breakthroughs in lithography or materials science. Competitors like TSMC and Intel may accelerate their own vertical integration strategies, while cloud providers and AI developers could fast-track systems designed to exploit these denser chips.
Bigger Picture
This development reflects a broader shift toward "More than Moore" strategies, where performance gains are achieved through architectural and packaging innovations rather than raw transistor scaling. It also highlights the growing role of IBM—once dominant in semiconductors—as a pioneer in high-performance computing niches rather than mainstream consumer chips.
